Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage or trapping layers or other physical phenomena, determine the data value of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular telephones, and removable memory modules, and the uses for flash memory continue to expand.
Conventional NAND memory architecture has even and odd rows adjacent to each other so that no adjacent word line is being programmed at the same time. Conventional read operations have a page read for even pages and a page read for odd pages. Not every cell can be read at the same time.
In NAND memories, coupling between the floating gates of cells, especially those on the same physical word lines of the memory, can be a problem. The problem continues to increase as the distance between floating gates decreases with decreasing memory sizes. As NAND flash memory is scaled, parasitic capacitance coupling between adjacent memory cell floating gates becomes a problem. Because of the capacitive coupling, the cells that are adjacent to a cell storing a charge are prone to having their threshold voltages (Vt) raised. If the adjacent cells have their threshold voltages raised too high, an unprogrammed cell might appear as being programmed. The increased capacitive coupling between the floating gates can affect the verification, reading, and erasing of adjacent cells.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for reduction of floating gate coupling in NAND memories.